4) Flow-Control Scheme: The flow control signal has to fulfill the following requirements:
• it has to be transmitted over a differential pair;
• for AC coupling it has to be DC free;
• it has to represent two states, receiver busy or ready.
We chose the flow control signal to be a square-wave because it is DC free and can easily be generated by clocked digital logic. The part of the FPGA which interfaces to the SerDes and performs the flow control is running at the same clock-speed as the parallel SerDes interfaces, e.g. 125MHz for a 2.5Gbit/s link. The receiver FPGA signals that it is ready to receive by generating a square-wave at half its clock frequency, i.e. 62.5MHz. If the receiver is running out of FIFO space it signals the sender to stop by generating a square-wave at an eighth of the clock frequency.
These signals can be easily decoded by the sender FPGA even though they are not synchronous to any of the sender FPGA's clock signals. It does so by counting the number of clock cycles the flow control signal keeps the same value. If this counter is one to three the sender keeps sending, if it counts to four or more the sender has to stop.
We have to know at what receiver FIFO fill-level we have to signal a stop condition to the sender. It is the sum of the forward channel and the back channel latency. According to [16] the SerDes has a total link latency of 38 + 107 = 145 bit times, giving 7.25 clock cycles, plus the line delay of the cable.
The flow-control back channel has a latency equal to the line delay plus two cycles for the synchronizer registers, plus 4 to 5 cycles to detect the stop state. This adds up to 14.25 cycles plus two line delays.
At a 2m maximum cable length this is 2 x 2m / 0.5c = 26.6 ns which is 3.3 cycles.2 Thus the total delay should be less than 18 cycles. The latest time to dispatch the flow control stop signal is thus when we have 18 words of the 16bit receiver FIFO remaining free.
5) 32bit word synchronization: When using 32bit addresses, two 16bit words have to be transferred per address. In order to detect the 32bit word boundary we define that the two 16bit words have to be sent back-to-back, with no IDLE characters in between. Once an IDLE character is seen, the receiver knows the 32bit word boundary. This allows 32bit words to also be sent back-to-back, once the receiver has seen a single IDLE character, thus the full bandwidth available can be used for address data.
D. FPGA implementation
We are using a Xilinx Spartan 3E series FPGA on the AEX board to link the three interface sections together. The PQ208 package chosen has a sufficient pin count for this system, while still allowing in-house assembly without reflow soldering.