While using common parallel AER interfaces for connecting to the locally attached chip, we use a novel serial AER interface with flow-control. With this interface running at a bit clock of up to 3.125GHz we achieve event rates of up to 78.125MHz for 32bit AEs.
The parallel AER interface allows for event rates of up to 20 to 30MHz. This is in practice reduced by the signal propagation delays induced by the PCB traces and especially when used with ribbon cables.
For sending monitored AEs to a PC and reading AEs to be sequenced back from it we implemented a USB2.0 interface. Here we achieved bandwidths of 40MB/s, only limited by the USB host-controller on the computer itself. This allows for an event rate of 5MHz with 64bit timestamped AEs.
Given the filtering capabilities of the FPGA's routing fabric we can easily select parts of the address space we are interested in for monitoring, and because of the large buffers for monitored data on the FPGA itself we can compensate for the fact that the FPGA to PC interface is a lot slower than the parallel and serial AER interfaces.
The very high speeds of the serial AER interface allows us to have very low latency in serial AER links, and these links allow for the construction of very large multi-chip address event systems, e.g. by daisy-chaining multiple AEX boards.
ACKNOWLEDGMENT
Some of the ideas presented in this work were inspired by dis¬cussions held at the Telluride Neuromorphic Engineering Workshop. Particularly helpful suggestions were provided by V. Dante, ISS Italy, and A. linares-Barranco, Universidad de Sevilla, Spain. We wish to also thank N. Felber, D-ITET ETHZ for supporting us regarding design aspects and U. Breu, C. Flaig, D. Flatz & A. Lehmann for proofreading. This work was supported in part by the EU grant DAISY (FP6-2005-015803).