Abstract— In recent years there have been an increasing number of research groups that have begun to develop multi-chip address-event systems.The communication protocol used to transmit signals between
these systems’components is based on the Address-Event Representation (AER). It is therefore important to have access to robust and reliable AER communication infrastructures for streamlining the systems’development and prototyping stages.
We propose an AER communication infrastructure that can be easily interfaced to workstations or laptops during a prototyping phase, and that can be embedded into compact and low-cost systems in the application phase. The infrastructure proposed uses a novel serial AER interface with flow-control, overcomes many of the drawbacks observed with previous solutions, and can achieve event rates of up to 78.125MHz for 32bit AEs.
I. INTRODUCTION
In recent years a new class of distributed multi-chip neuromorphic systems have emerged, e.g. [1]–[4].Thesesystems are typically composed of one or more neuromorphic sensors (e.g. [5], [6]), tional architectures, often based on networks of silicon neurons and synapses e.g. [7],and potentially of interfaces to robotic actuators for implementing real-time sensory-processing behaving systems.
A.The Address-Event Representation
Multiple researchgroups are developing a wide variety of multi-chip neuromorphic systems in parallel. The characteristic that all these systems have in common is the data representation and the communication protocol used. Each component in these systems can receive and transmit information using the Address-Event Representation (AER) [8], [9] communication protocol. In this representation, input and output signals are real-time digital events that carry analog information in their temporal relationships (inter-spike intervals). Each event is represented by a binary word encoding the address of the sending node. Output signals of sending elements are converted into streams of Address-Events (e.g. using pulse-frequency modulation in the case of silicon neurons), and multiplexed onto an asynchronous digital bus.