哪位程序高手帮我用VHDL语言设计一个8线—3线优先编码器，必须执行正确的，谢谢！

Question

如题所述

Answer 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity p_encoder is
port(st,in0,in1,in2,in3,in4,in5,in6,in7:IN bit;
yex,ys,y0,y1,y2:out bit);
end p_encoder;
architecture rtl of p_encoder is
signal tmp_in:bit_vector(7 downto 0);
signal tmp_out:bit_vector(4 downto 0);
begin
tmp_in <=in7&in6&in5&in4&in3&in2&in1&in0;
process(st,tmp_in)
begin
if(st='0')then
if(tmp_in="11111111")then
tmp_out<="11110";
elsif(tmp_in(7)='0')then
tmp_out<="00001";
elsif(tmp_in(6)='0')then
tmp_out<="00101";
elsif(tmp_in(5)='0')then
tmp_out<="01001";
elsif(tmp_in(4)='0')then
tmp_out<="01101";
elsif(tmp_in(3)='0')then
tmp_out<="10001";
elsif(tmp_in(2)='0')then
tmp_out<="10101";
elsif(tmp_in(1)='0')then
tmp_out<="11001";
elsif(tmp_in(0)='0')then
tmp_out<="11101";
end if;
else
tmp_out <= "11111";
end if;
ys<=tmp_out(0);yex<=tmp_out(1);y0<=tmp_out(2);y1<=tmp_out(3);y2<=tmp_out(4);
end process;
end rtl;

Answer 2

哪位程序高手帮我用VHDL语言设计一个8线—3线优先…3119