VHDL编译错误

Question

这是我的VHDL源程序：
--
-- file: p2r_CordicPipe.vhd
-- author: Richard Herveille
-- rev. 1.0 initial release

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity p2r_CordicPipe is
generic(
WIDTH : natural := 16;
PIPEID : natural := 1
);
port(
clk : in std_logic;
ena : in std_logic;

Xi : in signed(WIDTH -1 downto 0);
Yi : in signed(WIDTH -1 downto 0);
Zi : in signed(19 downto 0);

Xo : out signed(WIDTH -1 downto 0);
Yo : out signed(WIDTH -1 downto 0);
Zo : out signed(19 downto 0)
);
end entity p2r_CordicPipe;

architecture dataflow of p2r_CordicPipe is

function CATAN(n :natural) return integer is
variable result :integer;
begin
case n is
when 0 => result := 16#020000#;
when 1 => result := 16#012E40#;
when 2 => result := 16#09FB4#;
when 3 => result := 16#05111#;
when 4 => result := 16#028B1#;
when 5 => result := 16#0145D#;
when 6 => result := 16#0A2F#;
when 7 => result := 16#0518#;
when 8 => result := 16#028C#;
when 9 => result := 16#0146#;
when 10 => result := 16#0A3#;
when 11 => result := 16#051#;
when 12 => result := 16#029#;
when 13 => result := 16#014#;
when 14 => result := 16#0A#;
when 15 => result := 16#05#;
when 16 => result := 16#03#;
when 17 => result := 16#01#;
when others => result := 16#0#;
end case;
return result;
end CATAN;

compatibility with Xilinx WebPack
function Delta(Arg : signed; Cnt : natural) return signed is
variable tmp : signed(Arg'range);
constant lo : integer := Arg'high -cnt +1;
begin
for n in Arg'high downto lo loop
tmp(n) := Arg(Arg'high);
end loop;
for n in Arg'high -cnt downto 0 loop
tmp(n) := Arg(n +cnt);
end loop;
return tmp;
end function Delta;

function AddSub(dataa, datab : in signed; add_sub : in std_logic) return signed is
begin
if (add_sub = '1') then
return dataa + datab;
else
return dataa - datab;
end if;
end;

--
-- ARCHITECTURE BODY
--
signal dX, Xresult : signed(WIDTH -1 downto 0);
signal dY, Yresult : signed(WIDTH -1 downto 0);
signal atan, Zresult : signed(19 downto 0);

signal Zneg, Zpos : std_logic;

begin

dX <= Delta(Xi, PIPEID);
dY <= Delta(Yi, PIPEID);
atan <= conv_signed( catan(PIPEID), 20);

-- generate adder structures
Zneg <= Zi(19);
Zpos <= not Zi(19);

-- xadd
Xresult <= AddSub(Xi, dY, Zneg);

-- yadd
Yresult <= AddSub(Yi, dX, Zpos);

-- zadd
Zresult <= AddSub(Zi, atan, Zneg);

gen_regs: process(clk)
begin
if(clk'event and clk='1') then
if (ena = '1') then
Xo <= Xresult;
Yo <= Yresult;
Zo <= Zresult;
end if;
end if;
end process;

end architecture dataflow;
VHDL编译出现Error:Unkown problem in c:\max2work\p2r_cordicpipe.vhd[%Cmn-A-UnexpectedCase,Unexpected case encounterted:SimpleSubtype;in vu_GetNthIndexRange.]
noski大侠,在compatibility with Xilinx WebPack 前加--后,用MAX PLUXII编译后依然出现上面错误.这是为什么?

Answer 1

我在QuartusII 里编译了你的程序，报错：
Error (10500): VHDL syntax error at p2r_CordicPipe.vhd.vhd(58) near text "compatibility"; expecting "begin", or a declaration statement
“compatibility with Xilinx WebPack ”这一行，你用的Xilinx器件，是不是应该用 ModleSim （参考http://www.edacn.net/bbs/thread-68737-1-1.html），而你用的Altera公司的MAX Plus II

Answer 2

楼主在：compatibility with Xilinx WebPack
这句前面加两个减号“--”注释掉就对了。那句不是VHDL语句。
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不得不补充一句，tangbin76229不要误导别人。p2r_CordicPipe.vhd在OpenCore上的源代码我也看过了，那句纯粹就是注释。
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回复楼主，我用的是ModelSim6.2，编译通过了。。。