求助！谁能帮我翻译一下下面的VHDL程序？

Question

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY speed IS
PORT(
clk :IN STD_LOGIC;
reset:IN STD_LOGIC;
start:IN STD_LOGIC;
stop :IN STD_LOGIC;
sp :IN STD_LOGIC_VECTOR(2 DOWNTO 0);
clkout:OUT STD_LOGIC
);
END speed;

ARCHITECTURE rtl OF speed IS
BEGIN
PROCESS(clk,reset,stop,start,sp)
TYPE state_type IS(s0,s1);
VARIABLE s_state:state_type;
VARIABLE cnt:integer RANGE 0 TO 28;
VARIABLE kinside:INTEGER RANGE 0 TO 30;
BEGIN
CASE sp IS
WHEN "000"=>kinside:=0;
WHEN "001"=>kinside:=28;
WHEN "010"=>kinside:=24;
WHEN "011"=>kinside:=20;
WHEN "100"=>kinside:=16;
WHEN "101"=>kinside:=12;
WHEN "110"=>kinside:=8;
WHEN "111"=>kinside:=4;
END CASE;

IF reset='1'THEN
s_state:=s0;

ELSIF clk'EVENT AND clk='1'THEN
CASE s_state IS
WHEN s0=>
cnt:=0;
clkout<='0';
IF start='1'THEN
s_state:=s1;
ELSE
s_state:=s0;
END IF;

WHEN s1=>
clkout<='0';
IF stop='1'THEN
s_state:=s0;
ELSIF sp="000"then
s_state:=s1;
ELSIF cnt=kinside THEN
cnt:=0;
clkout<='1';
s_state:=s1;
ELSE
cnt:=cnt+1;
s_state:=s1;
END IF;
END CASE;
END IF;
END PROCESS;
END rtl;
能不能更详细点?? 谢谢

Answer 1

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY speed IS
PORT(
clk :IN STD_LOGIC;
reset:IN STD_LOGIC;
start:IN STD_LOGIC;
stop :IN STD_LOGIC;
sp :IN STD_LOGIC_VECTOR(2 DOWNTO 0);
clkout:OUT STD_LOGIC---输出信号
);
END speed;

ARCHITECTURE rtl OF speed IS
BEGIN
PROCESS(clk,reset,stop,start,sp) ---进程定只要一个其中一个信号有变化就启动进程
TYPE state_type IS(s0,s1);
VARIABLE s_state:state_type;
VARIABLE cnt:integer RANGE 0 TO 28;
VARIABLE kinside:INTEGER RANGE 0 TO 30;
BEGIN
CASE sp IS
WHEN "000"=>kinside:=0;
WHEN "001"=>kinside:=28;
WHEN "010"=>kinside:=24;
WHEN "011"=>kinside:=20;
WHEN "100"=>kinside:=16;
WHEN "101"=>kinside:=12;
WHEN "110"=>kinside:=8;
WHEN "111"=>kinside:=4;
END CASE;

IF reset='1'THEN -----异步清零，即时返回到状态1
s_state:=s0;

ELSIF clk'EVENT AND clk='1'THEN ---当信号上升沿到来到来启动
CASE s_state IS ------选择语句
WHEN s0=> ----状态0时执行此语句
cnt:=0;
clkout<='0'; -----输出时钟置低
IF start='1'THEN
s_state:=s1; -----如果“start” 有效转到状态1
ELSE
s_state:=s0; ------否则还是原始状态
END IF;

WHEN s1=> ----状态1时执行此语句
clkout<='0';
IF stop='1'THEN ---若此时停止信号有效，则回到状态0
s_state:=s0;
ELSIF sp="000"then -----我就不知道你的输入sp信号是什么意思，sp为“000”则在reset无效，start有效，stop还未有效时，在在状态1出等待

s_state:=s1;
ELSIF cnt=kinside THEN ------否则sp作为输入信号控制对不同- ------------输入的值意味着低电平的持续时间（时钟脉冲，之后就- -------是高电平了，只致reset，stop，或start 变化后回到状态0
cnt:=0;
clkout<='1';
s_state:=s1;
ELSE
cnt:=cnt+1;-----加1直至满足cnt=kinside
s_state:=s1;
END IF;
END CASE;
END IF;
END PROCESS;
END rtl;

Answer 2

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY speed IS
PORT( --信号定义
clk :IN STD_LOGIC;--时钟信号
reset:IN STD_LOGIC;--复位信号
start:IN STD_LOGIC;--开始信号
stop :IN STD_LOGIC;--停止
sp :IN STD_LOGIC_VECTOR(2 DOWNTO 0);--脉冲=0
clkout:OUT STD_LOGIC--时钟输出信号
);
END speed;

ARCHITECTURE rtl OF speed IS
BEGIN
PROCESS(clk,reset,stop,start,sp)
TYPE state_type IS(s0,s1); --两个状态
VARIABLE s_state:state_type;
VARIABLE cnt:integer RANGE 0 TO 28;
VARIABLE kinside:INTEGER RANGE 0 TO 30;
BEGIN
CASE sp IS
WHEN "000"=>kinside:=0; --当sp=000的时候，kinside=0
WHEN "001"=>kinside:=28; --当sp=001的时候，kinside=28
WHEN "010"=>kinside:=24; ...
WHEN "011"=>kinside:=20; ...
WHEN "100"=>kinside:=16; ..
WHEN "101"=>kinside:=12; ...
WHEN "110"=>kinside:=8; ..
WHEN "111"=>kinside:=4; ..
END CASE;

IF reset='1'THEN -- 当reset=1的时候进入状态S0 s_state:=s0;

ELSIF clk'EVENT AND clk='1'THEN
CASE s_state IS
WHEN s0=> --状态S0
cnt:=0;
clkout<='0';
IF start='1'THEN -- 当Start信号有效时，进状态S1
s_state:=s1;
ELSE
s_state:=s0; --否则保持在状态S0
END IF;

WHEN s1=> --状态S0
clkout<='0';
IF stop='1'THEN -- 当Start信号有效时,进入状态S0
s_state:=s0;
ELSIF sp="000"then --否则当sp=000时，进入状态S1
s_state:=s1;
ELSIF cnt=kinside THEN--否则当cnt=kinside时，输出下面的
cnt:=0;
clkout<='1';
s_state:=s1;
ELSE --要是都不是上面几个条件，就保持在S1状态，cnt加1
cnt:=cnt+1;
s_state:=s1;
END IF;
END CASE;
END IF;
END PROCESS;
END rtl;

Answer 3

这是一个简单的脉冲序列发生器，于clk相比，根据外部输入的SP的情况，决定多少个（0，4，8，12，16，20，...）CLK之后产生一个脉冲。