用VHDL实现4-16译码器

Question

用VHDL语言就可以了

Answer 1

library ieee;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY decode4-16 IS
PORT(a,b,c,d:IN STD_LOGIC;
q:BUFFER STD_LOGIC_VECTOR(15 DOWNTO 0));
END decode4-16 ;
architecture behave of decode4-16 is
signal indata:std_logic_vector(2 downto 0);
begin
indata<=c&b&a;
process(indata)
begin
case indata is
when “0000”=>y<=”1111111111111110”;
when “0001”=>y<=”1111111111111101”;
when “0010”=>y<=”1111111111111011”;
when “0011”=>y<=”1111111111110111”;
when “0100”=>y<=”1111111111101111”;
when “0101”=>y<=”1111111111011111”;
when “0110”=>y<=”1111111110111111”;
when “0111”=>y<=”1111111101111111”;
when “1000”=>y<=”1111111011111111”;
when “1001”=>y<=”1111110111111111”;
when “1010”=>y<=”1111101111111111”;
when “1011”=>y<=”1111011111111111”;
when “1100”=>y<=”1110111111111111”;
when “1101”=>y<=”1101111111111111”;
when “1110”=>y<=”1011111111111111”;
when “1111”=>y<=”0111111111111111”;
when others=>y<=”xxxxxxxxxxxxxxxx”;
end case;
end process;
end behave;本回答被提问者采纳

Answer 2

最简单的，没有时钟，请雅正
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Decoder is
Port (
DIN : in std_logic_vector(3 downto 0);
DOUT : out std_logic_vector(15 downto 0)
);
end Decoder;
architecture rtl of Decoder is
begin
process (DIN) begin
case(DIN) is
when "0000" => DOUT <= "0111111111111111";
when "0001" => DOUT <= "1011111111111111";
when "0010" => DOUT <= "1101111111111111";
when "0011" => DOUT <= "1110111111111111";
when "0100" => DOUT <= "1111011111111111";
when "0101" => DOUT <= "1111101111111111";
when "0110" => DOUT <= "1111110111111111";
when "0111" => DOUT <= "1111111011111111";
when "1000" => DOUT <= "1111111101111111";
when "1001" => DOUT <= "1111111110111111";
when "1010" => DOUT <= "1111111111011111";
when "1011" => DOUT <= "1111111111101111";
when "1100" => DOUT <= "1111111111110111";
when "1101" => DOUT <= "1111111111111011";
when "1110" => DOUT <= "1111111111111101";
when "1111" => DOUT <= "1111111111111110";
when others => DOUT <= "1111111111111111";
end case;
end process;
end rtl;本回答被网友采纳

Answer 3

用循环写更简单，而且楼上的把输出的左右次序弄反了吧？一般我们习惯当DIN="0000"时，DOUT(0) = '0'

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity Decoder is
port (
DIN : in std_logic_vector(3 downto 0);
DOUT_n : out std_logic_vector(15 downto 0)
);
end Decoder;

architecture Decoder_arch of Decoder is

begin

gen : for i in 0 to 15 generate
DOUT_n(i) <= '0' when DIN = i else '1';
end generate;

end Decoder_arch;