正确答案！
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity yimaqi is
port(a0,a1,a2,a3:in std_logic;
y:out std_logic_vector(15 downto 0));
end yimaqi;
architecture one of yimaqi is
signal temp:std_logic_vector(3 downto 0);
begin
temp<=a0&a1&a2&a3;
process(temp)
begin
case temp is
when "0000"=>y<="1111111111111110";
when "0001"=>y<="1111111111111101";
when "0010"=>y<="1111111111111011";
when "0011"=>y<="1111111111110111";
when "0100"=>y<="1111111111101111";
when "0101"=>y<="1111111111011111";
when "0110"=>y<="1111111110111111";
when "0111"=>y<="1111111101111111";
when "1000"=>y<="1111111011111111";
when "1001"=>y<="1111110111111111";
when "1010"=>y<="1111101111111111";
when "1011"=>y<="1111011111111111";
when "1100"=>y<="1110111111111111";
when "1101"=>y<="1101111111111111";
when "1110"=>y<="1011111111111111";
when "1111"=>y<="0111111111111111";
when others=>y<="XXXXXXXXXXXXXXXX";
end case;
end process;
end one;