数字钟设计用VHDL语言实现你怎么做的

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推荐答案 2010-07-02

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY TZKZQ IS

PORT(KEY: IN STD_LOGIC_VECTOR(1 DOWNTO 0); --æé®ä¿¡å·

CLK_KEY: IN STD_LOGIC; --é®çæ«æä¿¡å·

MAX_DAYS:IN STD_LOGIC_VECTOR(4 DOWNTO 0); --æ¬ææå¤§å¤©æ°

SEC_EN,MIN_EN,HOUR_EN,DAY_EN,MON_EN,YEAR_EN,WEEK_EN:OUT STD_LOGIC; --å¼æ¥å¹¶è¡ç½®ä½ä½¿è½

HOUR_CUR:IN STD_LOGIC_VECTOR(4 DOWNTO 0);

MIN_CUR,SEC_CUR:IN STD_LOGIC_VECTOR(5 DOWNTO 0);

YEAR_CUR:IN STD_LOGIC_VECTOR(6 DOWNTO 0);

MON_CUR :IN STD_LOGIC_VECTOR(3 DOWNTO 0);

DAY_CUR :IN STD_LOGIC_VECTOR(4 DOWNTO 0);

WEEK_CUR:IN STD_LOGIC_VECTOR(2 DOWNTO 0);

SEC,MIN:BUFFER STD_LOGIC_VECTOR(5 DOWNTO 0);

HOUR:BUFFER STD_LOGIC_VECTOR(4 DOWNTO 0);

DAY :BUFFER STD_LOGIC_VECTOR(4 DOWNTO 0);

MON :BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);

YEAR:BUFFER STD_LOGIC_VECTOR(6 DOWNTO 0);

WEEK:BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0));

END ENTITY TZKZQ;

ARCHITECTURE ART OF TZKZQ IS

TYPE STATETYPE IS (NORMAL,SEC_SET,MIN_SET,HOUR_SET,DAY_SET,MON_SET,

YEAR_SET,WEEK_SET);

SIGNAL MODE:STATETYPE;

BEGIN

PROCESS(KEY,CLK_KEY)

BEGIN

IF CLK_KEY'EVENT AND CLK_KEY='1' THEN

IF KEY="01" THEN

SEC_EN<='1';MIN_EN<='1';HOUR_EN<='1';

DAY_EN<='1';MON_EN<='1';YEAR_EN<='1';

WEEK_EN<='1';

CASE MODE IS

WHEN NORMAL => MODE<=SEC_SET;SEC<=SEC_CUR;SEC_EN<='0';

WHEN SEC_SET => MODE<=MIN_SET;MIN<=MIN_CUR;SEC_EN<='1';MIN_EN<='0';

WHEN MIN_SET => MODE<=HOUR_SET;HOUR<=HOUR_CUR;MIN_EN<='1';HOUR_EN<='0';

WHEN HOUR_SET=> MODE<=DAY_SET;DAY<=DAY_CUR;HOUR_EN<='1';DAY_EN<='0';

WHEN DAY_SET => MODE<=MON_SET;MON<=MON_CUR;DAY_EN<='1';MON_EN<='0';

WHEN MON_SET => MODE<=YEAR_SET;YEAR<=YEAR_CUR; MON_EN<='1';

YEAR_EN<='0';

WHEN YEAR_SET => MODE<=WEEK_SET;WEEK<=WEEK_CUR;YEAR_EN<='1';WEEK_EN<='0';

WHEN WEEK_SET => MODE<=NORMAL;

END CASE;

ELSIF KEY="10" THEN --å¦ææä¸è°æ´é®ï¼åèªå

CASE MODE IS

WHEN SEC_SET => SEC_EN<='0';

--å¼æ¥å¹¶è¡ç½®ä½ä½¿è½ææ

IF SEC="111011" THEN SEC<="000000";

--å¦æç§è®¡æ°å°59ï¼è¿åå°0éæ°è®¡æ°

ELSE SEC<=SEC+1; --å¦åç»§ç»è®¡æ°

END IF;

WHEN MIN_SET => MIN_EN<='0';

IF MIN="111011" THEN MIN<="000000";

ELSE MIN<=MIN+1;

END IF;

WHEN HOUR_SET=> HOUR_EN<='0';

IF HOUR="11000" THEN HOUR<="00000";

ELSE HOUR<=HOUR+1;

END IF;

WHEN DAY_SET => DAY_EN<='0';

IF DAY=MAX_DAYS THEN DAY<="00001";

ELSE DAY<=DAY+1;

END IF;

WHEN WEEK_SET=> WEEK_EN<='0';

IF WEEK="111" THEN WEEK<="001";

ELSE WEEK<=WEEK+1;

END IF;

WHEN OTHERS=>NULL;

END CASE;

END IF;

END PROCESS;

END ARCHITECTURE ART;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CNT60 IS

PORT(LD: IN STD_LOGIC;

CLK: IN STD_LOGIC;

DATA: IN STD_LOGIC_VECTOR(5 DOWNTO 0);

NUM: BUFFER STD_LOGIC_VECTOR(5 DOWNTO 0);

CO: OUT STD_LOGIC);

END ENTITY CNT60;

ARCHITECTURE ART OF CNT60 IS

BEGIN

PROCESS(CLK,LD) IS

BEGIN

IF(LD='0') THEN

NUM<=DATA;

ELSIF CLK'EVENT AND CLK='1' THEN

IF NUM="111011" THEN --59

NUM<="000000";CO<='1';

ELSE

NUM<=NUM+1;CO<='0';

END IF;

END PROCESS;

END ARCHITECTURE ART;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CNT60 IS

PORT(LD: IN STD_LOGIC;

CLK: IN STD_LOGIC;

DATA: IN STD_LOGIC_VECTOR(5 DOWNTO 0);

NUM: BUFFER STD_LOGIC_VECTOR(5 DOWNTO 0);

CO: OUT STD_LOGIC);

END ENTITY CNT60;

ARCHITECTURE ART OF CNT60 IS

BEGIN

PROCESS(CLK,LD) IS

BEGIN

IF(LD='0') THEN

NUM<=DATA;

ELSIF CLK'EVENT AND CLK='1' THEN

IF NUM="111011" THEN --59

NUM<="000000";CO<='1';

ELSE

NUM<=NUM+1;CO<='0';

END IF;

END PROCESS;

END ARCHITECTURE ART;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CNT24 IS

PORT(LD: IN STD_LOGIC;

CLK: IN STD_LOGIC;

DATA: IN STD_LOGIC_VECTOR(4 DOWNTO 0);

NUM: BUFFER STD_LOGIC_VECTOR(4 DOWNTO 0);

CO: OUT STD_LOGIC);

END ENTITY CNT24;

ARCHITECTURE ART OF CNT24 IS

BEGIN

PROCESS(CLK,LD) IS

BEGIN

IF(LD='0') THEN

NUM<=DATA;

ELSIF CLK'EVENT AND CLK='1' THEN

IF NUM="11000" THEN --24

NUM<="00000";CO<='1';

ELSE

NUM<=NUM+1;CO<='0';

END IF;

END PROCESS;

END ARCHITECTURE ART;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CNT30 IS

PORT(LD:IN STD_LOGIC;

CLK:IN STD_LOGIC;

NIAN:IN STD_LOGIC_VECTOR(6 DOWNTO 0);

YUE :IN STD_LOGIC_VECTOR(3 DOWNTO 0);

DATA:IN STD_LOGIC_VECTOR(4 DOWNTO 0);

NUM:BUFFER STD_LOGIC_VECTOR(4 DOWNTO 0);

MAX_DAYS:OUT STD_LOGIC_VECTOR(4 DOWNTO 0);

CO:OUT STD_LOGIC);

END ENTITY CNT30;

ARCHITECTURE ART OF CNT30 IS

SIGNAL TOTAL_DAYS:STD_LOGIC_VECTOR(4 DOWNTO 0);

BEGIN

PROCESS(CLK,LD) IS

VARIABLE IS_RUNNIAN:STD_LOGIC;

BEGIN

CASE NIAN IS

WHEN "0000000" => IS_RUNNIAN:='1'; --0

WHEN "0000100" => IS_RUNNIAN:='1'; --4

WHEN "0001000" => IS_RUNNIAN:='1'; --8

WHEN "0001100" => IS_RUNNIAN:='1'; --12

WHEN "0010000" => IS_RUNNIAN:='1'; --16

WHEN "0010100" => IS_RUNNIAN:='1'; --20

WHEN "0011000" => IS_RUNNIAN:='1'; --24

WHEN "0011100" => IS_RUNNIAN:='1'; --28

WHEN "0100000" => IS_RUNNIAN:='1'; --32

WHEN "0100100" => IS_RUNNIAN:='1'; --36

WHEN "0101000" => IS_RUNNIAN:='1'; --40

WHEN "0101100" => IS_RUNNIAN:='1'; --44

WHEN "0110000" => IS_RUNNIAN:='1'; --48

WHEN "0110100" => IS_RUNNIAN:='1'; --52

WHEN "0111000" => IS_RUNNIAN:='1'; --56

WHEN "0111100" => IS_RUNNIAN:='1'; --60

WHEN "1000000" => IS_RUNNIAN:='1'; --64

WHEN "1000100" => IS_RUNNIAN:='1'; --68

WHEN "1001000" => IS_RUNNIAN:='1'; --72

WHEN "1001100" => IS_RUNNIAN:='1'; --76

WHEN "1010000" => IS_RUNNIAN:='1'; --80

WHEN "1010100" => IS_RUNNIAN:='1'; --84

WHEN "1011000" => IS_RUNNIAN:='1'; --88

WHEN "1011100" => IS_RUNNIAN:='1'; --92

WHEN "1100000" => IS_RUNNIAN:='1'; --96

WHEN OTHERS => IS_RUNNIAN:='0';

END CASE;

CASE YUE IS

WHEN "0001" => TOTAL_DAYS<="11111"; --1

WHEN "0011" => TOTAL_DAYS<="11111"; --3

WHEN "0101" => TOTAL_DAYS<="11111"; --5

WHEN "0111" => TOTAL_DAYS<="11111"; --7

WHEN "1000" => TOTAL_DAYS<="11111"; --8

WHEN "1010" => TOTAL_DAYS<="11111"; --10

WHEN "1100" => TOTAL_DAYS<="11111"; --12

WHEN "0100" => TOTAL_DAYS<="11110"; --4

WHEN "0110" => TOTAL_DAYS<="11110"; --6

WHEN "1001" => TOTAL_DAYS<="11110"; --9

WHEN "1011" => TOTAL_DAYS<="11110"; --11

WHEN "0010" =>

IF (IS_RUNNIAN='1') THEN

TOTAL_DAYS<="11101";

ELSE

TOTAL_DAYS<="11100";

END IF;

WHEN OTHERS=>NULL;

END CASE;

IF(LD='0') THEN

NUM<=DATA;

ELSIF CLK'EVENT AND CLK='1' THEN

MAX_DAYS<=TOTAL_DAYS;

IF NUM=TOTAL_DAYS THEN --99

NUM<="00001";CO<='1';

ELSE

NUM<=NUM+1;CO<='0';

END IF;

END PROCESS;

END ARCHITECTURE ART;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CNT7 IS

PORT(LD: IN STD_LOGIC;

CLK: IN STD_LOGIC;

DATA: IN STD_LOGIC_VECTOR(2 DOWNTO 0);

NUM: BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0));

END ENTITY CNT7;

ARCHITECTURE ART OF CNT7 IS

BEGIN

PROCESS(CLK,LD) IS

BEGIN

IF(LD='0') THEN

NUM<=DATA;

ELSIF CLK'EVENT AND CLK='1' THEN

IF NUM="111" THEN --7

NUM<="000";

ELSE

NUM<=NUM+1;

END IF;

END PROCESS;

END ARCHITECTURE ART;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CNT12 IS

PORT(LD: IN STD_LOGIC;

CLK: IN STD_LOGIC;

DATA: IN STD_LOGIC_VECTOR(3 DOWNTO 0);

NUM: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);

CO: OUT STD_LOGIC);

END ENTITY CNT12;

ARCHITECTURE ART OF CNT12 IS

BEGIN

PROCESS(CLK,LD) IS

BEGIN

IF(LD='0') THEN

NUM<=DATA;

ELSIF CLK'EVENT AND CLK='1' THEN

IF NUM="1100" THEN --12

NUM<="0000";CO<='1';

ELSE

NUM<=NUM+1;CO<='0';

END IF;

END PROCESS;

END ARCHITECTURE ART;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CNT99 IS

PORT(LD: IN STD_LOGIC;

CLK: IN STD_LOGIC;

DATA: IN STD_LOGIC_VECTOR(6 DOWNTO 0);

NUM: BUFFER STD_LOGIC_VECTOR(6 DOWNTO 0));

END ENTITY CNT99;

ARCHITECTURE ART OF CNT99 IS

BEGIN

PROCESS(CLK,LD) IS

BEGIN

IF(LD='0') THEN

NUM<=DATA;

ELSIF CLK'EVENT AND CLK='1' THEN

IF NUM="1100011" THEN --12

NUM<="0000000";

ELSE

NUM<=NUM+1;

END IF;

END PROCESS;

END ARCHITECTURE ART;

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第1个回答 2010-07-08

EDA设计——多功能数字钟
由于实验室cpld芯片为 ACEC1K EP1K10TC100-3 内部资源不是很丰富，故设计时应考虑节省系统资源开销，采用原理图互联，自顶向下方式设计方便快捷、可读性好，但芯片之间互联必然会增加系统内部数据寄存器。故在设计之初，就考虑到用编程方法实现。本设计采用VHDL语言编写，整个系统共用一个程序语言描述，在最大程度上实现了数据的共用。经过最后编译，调试，下载测试完成后，达到了实验要求
电路接口：
alarm——蜂鸣器接口
row[3,2,1,0]——矩阵键盘行
col[3,2,1,0]——矩阵键盘列
sel[2,1,0]——数码管为选接口
sg[6,5,4,3,2,1,0]——数码管断码接口
clk——接1024hz信号
代码如下

VhdL代码及解释：
library ieee;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all;
entity eda_clk9 is
port( clk : in std_logic ;--时钟输入
alarm : out std_logic;--闹钟输出
row : inout std_logic_vector(3 downto 0);--矩阵键盘行输入
col : inout std_logic_vector(3 downto 0);--矩阵键盘列输出
sel : out std_logic_vector(2 downto 0);--显示位选码输出
sg : out std_logic_vector(6 downto 0));--显示段码输出
end entity eda_clk9;
architecture one of eda_clk9 is
signal clk_1:std_logic ;--500hz信号
signal clk_2:std_logic ;--100hz信号
signal alarm_flag :std_logic ;--闹钟标志位
signal stat : std_logic_vector(2 downto 0) ;--状态标志向量
signal buff0,buff1,buff2,buff3,buff4,buff5,buff6,buff7 :
std_logic_vector(3 downto 0);--显示缓冲
signal input0,input1,input2,input3,input4,input5 :
std_logic_vector(3 downto 0);--输入缓冲
signal keyr,keyc : std_logic_vector(3 downto 0);--键盘行列缓存
signal kcount : std_logic_vector(2 downto 0);--键盘程序计数
signal kflag1,kflag2 : std_logic;--键盘标志信号
signal key_val : std_logic_vector(3 downto 0) ;--键盘缓存
signal kf : std_logic ;--键值赋值标志
signal keyflag : std_logic ;--按键信号
signal input_n : integer range 7 downto 0;--输入计数
signal dis_word : std_logic_vector(3 downto 0);--显示缓存
signal dis_n : std_logic_vector(2 downto 0);--显示计数
signal clk_count: std_logic_vector(8 downto 0);--时钟计数
signal fp500 : std_logic_vector(4 downto 0);--500hz分频中介变量
signal fp100 : std_logic_vector(6 downto 0);--100hz分频中介变量
signal clk_sec_1 : std_logic_vector(3 downto 0);--时钟各位
signal clk_sec_2 : std_logic_vector(3 downto 0);
signal clk_min_1 : std_logic_vector(3 downto 0);
signal clk_min_2 : std_logic_vector(3 downto 0);
signal clk_hou_1 : std_logic_vector(3 downto 0);
signal clk_hou_2 : std_logic_vector(3 downto 0);
signal alarm_sec_1 : std_logic_vector(3 downto 0);--闹钟各位
signal alarm_sec_2 : std_logic_vector(3 downto 0);
signal alarm_min_1 : std_logic_vector(3 downto 0);
signal alarm_min_2 : std_logic_vector(3 downto 0);
signal alarm_hou_1 : std_logic_vector(3 downto 0);
signal alarm_hou_2 : std_logic_vector(3 downto 0);
signal stop_mil_1 : std_logic_vector(3 downto 0);--秒表各位
signal stop_mil_2 : std_logic_vector(3 downto 0);
signal stop_sec_1 : std_logic_vector(3 downto 0);
signal stop_sec_2 : std_logic_vector(3 downto 0);
signal stop_min_1 : std_logic_vector(3 downto 0);
signal stop_min_2 : std_logic_vector(3 downto 0);
signal stop_fg : std_logic ;
begin
input_1 : process(clk_1) --记录按键过程中时间
begin
if(clk_1'event and clk_1='1')
then kcount<=kcount+1;--上升沿加一
end if;
end process input_1;
input_2 : process(clk_1) --两次扫描键盘判断是否按键
begin
if(clk_1'event and clk_1='1') then--上升沿触发
if(kcount=0) then
row<="1111";--全盘扫描
col<="0000";
elsif(kcount=1) then
keyr<=row;--读行扫描信号
elsif(kcount=2) then
row<="0000";--再次扫描
col<="1111";
elsif(kcount=3) then
keyc<=col;--读列三秒信号
end if;
end if;
end process input_2;
input_3: process(clk_1) --设置按键标志位
begin
if(clk_1'event and clk_1='1') then--上升沿触发
if(kcount=4 and keyr="1111") then--第四时钟，无按键
kflag1<='0';--清标志位
elsif(kcount=4) then
kflag1<='1';--置标值为
end if;
kflag2<=kflag1;--缓存
end if;
end process input_3;
input_4 : process(clk_1) --判断按键，计算键码，设置按键信号
variable temp : std_logic_vector(3 downto 0) ;--定义中间计算缓存变量
begin
if(clk_1'event and clk_1='1') then
if(kcount=5 and kflag1='1' and kflag2='0') then --有按键
temp:= "0000" ;--计算缓存清零
case keyc is--键盘行值
when "1110" => temp :=temp ;
when "1101" => temp :=temp + 1;
when "1011" => temp :=temp + 2;
when "0111" => temp :=temp + 3;
when others =>null;
end case;
case keyr is--键盘列值
when "1110" => temp:=temp ;
when "1101" => temp:=temp+4;
when "1011" => temp:=temp+8;
when "0111" => temp:=temp+12;
when others => null;
end case;
kf <= '1';--置按键信号为
key_val<=temp;
else kf <= '0';--清按键信号为
end if;
if kf = '1'--按键成功赋值后产生一按键标志脉冲keyflag
then keyflag <= '1' ;
kf <='0';
else keyflag <= '0';
end if;
end if;
end process input_4 ;
input_5: process(keyflag) --循环六次来输入时间，闹钟初值
begin
if keyflag'event and (keyflag = '1') then
if stat(1) = '1' and key_val <10 then--判断为按键状态，且按键为数值键
input_n<=input_n+1;
case input_n is--分别对应输入次数存入不同的输入缓冲
when 0 => input0<=key_val;
when 1 => input1<=key_val;
when 2 => input2<=key_val;
when 3 => input3<=key_val;
when 4 => input4<=key_val;
when 5 => input5<=key_val;
when others => input_n <= 0;--为下次输入做准备
end case;
else input_n <= 0 ;--为输入做准备
input0 <= "1011" ;--显示“--------”
input1 <= "1011" ;
input2 <= "1011" ;
input3 <= "1011" ;
input4 <= "1011" ;
input5 <= "1011" ;
end if;
end if;
end process input_5 ;
dis_1 : process(clk_1)--此进程为显示buff0~7的值在数码管上，显示方式为逐位扫描显示。
variable dis_word : std_logic_vector(3 downto 0);
begin
if clk_1'event and clk_1 = '1' then --上升沿触发
dis_n <= dis_n +1 ; --下一次显示下一位数码
case dis_n is --根据显示位数取对应的位的数值
when "000" => dis_word := buff0 ;
when "001" => dis_word := buff1 ;
when "010" => dis_word := buff2 ;
when "011" => dis_word := buff3 ;
when "100" => dis_word := buff4 ;
when "101" => dis_word := buff5 ;
when "110" => dis_word := buff6 ;
when "111" => dis_word := buff7 ;
when others => null ;
end case ;
sel <= dis_n;--送出按位显示的位选信号
case dis_word is--对应数值译码
when "0000" => sg <= "0111111";
when "0001" => sg <= "0000110";
when "0010" => sg <= "1011011";
when "0011" => sg <= "1001111";
when "0100" => sg <= "1100110";
when "0101" => sg <= "1101101";
when "0110" => sg <= "1111101";
when "0111" => sg <= "0000111";
when "1000" => sg <= "1111111";
when "1001" => sg <= "1101111";
when "1010" => sg <= "1110111";
when "1011" => sg <= "1000000";
when "1100" => sg <= "0111001";
when "1101" => sg <= "1011110";
when "1110" => sg <= "1111001";
when "1111" => sg <= "1110001";
when others =>null;
end case ;
end if;
end process dis_1;
dis_2 : process (stat) --根据系统状态显示不同的内容
begin
case stat is
when "000" =>--显示时间状态
buff7 <= clk_sec_1;
buff6 <= clk_sec_2;
buff4 <= clk_min_1;
buff3 <= clk_min_2;
buff1 <= clk_hou_1;
buff0 <= clk_hou_2;
buff2 <= "1011";
buff5 <= "1011";
when "001" =>--显示闹钟状态
buff7 <= alarm_sec_1;
buff6 <= alarm_sec_2;
buff4 <= alarm_min_1;
buff3 <= alarm_min_2;
buff1 <= alarm_hou_1;
buff0 <= alarm_hou_2;
buff2 <= "1011";
buff5 <= "1011";
when "010" |"011" =>--输入状态显示
buff7 <= input5;
buff6 <= input4;
buff4 <= input3;
buff3 <= input2;
buff1 <= input1;
buff0 <= input0;
when "100" =>--秒表显示状态
buff7 <= stop_mil_1;
buff6 <= stop_mil_2;
buff4 <= stop_sec_1;
buff3 <= stop_sec_2;
buff1 <= stop_min_1;
buff0 <= stop_min_2;
buff2 <= "1011";
buff5 <= "1011";
when others => null ;
end case ;
end process dis_2;
clock:process (clk_1)--时钟进程
begin
if clk_1'event and clk_1='1' then --上升沿触发
if clk_count = 500 --500hz分频后得1hz
then clk_count <= "000000000";
else clk_count <= clk_count + 1;
end if;
if stat = "010" and input_n >5 then --若在调时状态，且输入5次后
clk_hou_2 <= input0 ;--将输入缓冲中的值放如计时初值中
clk_hou_1 <= input1 ;
clk_min_2 <= input2 ;
clk_min_1 <= input3 ;
clk_sec_2 <= input4 ;
clk_sec_1 <= input5 ;
elsif clk_count = 0 then --达到一秒后，秒位加一
clk_sec_1 <= clk_sec_1 + 1;
elsif clk_sec_1 = "1010" then --如果秒位为10清零
clk_sec_1 <= "0000";
clk_sec_2 <= clk_sec_2 +1 ; --同时秒的十位加一
elsif clk_sec_2 = "0110" then --如果秒十位为6
clk_min_1 <= clk_min_1 +1; --分钟个位加一
clk_sec_2 <= "0000";
elsif clk_min_1 = "1010" then --分个位为10时清零
clk_min_1 <= "0000";
clk_min_2 <= clk_min_2 +1 ; --分十位加一
elsif clk_min_2 = "0110" then --分十位为6时
clk_hou_1 <= clk_hou_1 +1; --小时个位加一
clk_min_2 <= "0000"; --分钟十为清零
elsif clk_hou_1 = "1010" then --小时个位为10清零
clk_hou_1 <= "0000";
clk_hou_2 <= clk_min_2 +1 ; --小时十为加一
elsif clk_hou_2 = "0010" and clk_hou_1 = "0100" then--达到24点时小时清零
clk_hou_1 <= "0000";
clk_hou_2 <= "0000";
elsif (clk_sec_2 > 5) or (clk_min_2 > 5) or (clk_hou_2 > 2) or ( (clk_hou_2 = 2 )and (clk_hou_1 > 3))
then clk_sec_1 <= "0000"; --设定时间非法时，设置为默认时间初值00:00:00
clk_sec_2 <= "0000";
clk_min_1 <= "0000";
clk_min_2 <= "0000";
clk_hou_1 <= "0000";
clk_hou_2 <= "0000";
end if;
end if;
end process clock;

naozhong_1 : process (clk_sec_1)
begin
if (clk_sec_1 = alarm_sec_1) and (clk_sec_2 = alarm_sec_2) and (clk_min_1 = alarm_min_1) and (clk_min_2 = alarm_min_2) and (clk_hou_1 = alarm_hou_1) and (clk_hou_2 = alarm_hou_2)
then alarm_flag <='1'; --时间到达闹钟时置闹钟位
elsif key_val = "1111" then --按闹钟设定15号键时关闭闹钟
alarm_flag <= '0';
end if;
end process naozhong_1 ;
naozhong_2 :process (clk_1)
begin--闹钟鸣叫进程
if alarm_flag = '1' then --没按关闭键
if clk_count < 200 then --长鸣
alarm <= '1';
elsif clk_count <300 then
alarm <= '0';
elsif clk_count <350 then--短鸣
alarm <= '1';
elsif clk_count <400 then
alarm <= '0';
elsif clk_count <450 then--短鸣
alarm <= '1';
else alarm <= '0';
end if;
else alarm <= '0';
end if;
end process naozhong_2 ;

main : process(keyflag)
begin--主控状态进程
if keyflag'event and keyflag = '1' then--有按键就触发
if input_n >5 then
stat <= "000" ; --若按键达到5次，则必从设定状态返回到时间显示状态
else case key_val is
when "1011" => stop_fg <= not (stop_fg) ; --秒表操作
when "1100" => stat <= "000"; -- 显示时间
when "1101" => stat <= "001"; -- 显示闹钟
when "1110" => stat <= "010"; -- 设定时间
when "1111" => stat <= "011"; -- 设定闹钟
when "1010" => stat <= "100"; -- 开启秒表
when others => null;
end case;
end if;
if stat = "011" and input_n >5 then --闹钟设定赋输入的初值
alarm_hou_2 <= input0 ;
alarm_hou_1 <= input1 ;
alarm_min_2 <= input2 ;
alarm_min_1 <= input3 ;
alarm_sec_2 <= input4 ;
alarm_sec_1 <= input5 ;
elsif (alarm_sec_2 > 5) or (alarm_min_2 > 5) or (alarm_hou_2 > 2) or ( (alarm_hou_2 = 2 )and (alarm_hou_1 > 3))
then alarm_hou_2 <= "0000"; --设定闹钟的时间非法时清零
alarm_hou_1 <= "0000";
alarm_min_2 <= "0000";
alarm_min_1 <= "0000";
alarm_sec_2 <= "0000";
alarm_sec_1 <= "0000";
end if;
end if;
end process main;
fengping : process (clk)
begin --12khz的时钟分频
if clk'event and clk = '1' then
if fp500 ="10111" then --计算为24 = 11000
fp500 <= "00000"; --500hz分频
clk_1 <= '1';
else
fp500 <= fp500 + 1;
clk_1 <= '0';
end if;
if fp100 = "1101001" then --计算为1201 = 1111000
fp100 <= "0000000"; --100hz分频
clk_2 <= '1';
else
fp100 <=fp100 + 1;
clk_2 <= '0';
end if;
end if;
end process fengping ;
stop : process (clk_2)
begin --秒表进程
if clk_2'event and (clk_2 = '1') then --上升沿触发
if stop_fg = '1' and stat(2) = '1' then--按键开始且为秒表状态
if stop_mil_1 = "1010" then--毫秒个位为10时清零
stop_mil_1 <= "0000" ;
else stop_mil_1 <= stop_mil_1 + 1;--否则加一
end if;
if stop_mil_2 = "1010" then--毫秒十位为10时清零
stop_mil_2 <= "0000";
elsif stop_mil_1 = "1010" then--由于信号延迟，毫秒个位为10时进位
stop_mil_2 <= stop_mil_2 + 1;
end if;
if stop_sec_1 = "1010" then--秒进位
stop_sec_1 <= "0000" ;
elsif stop_mil_2 = "1010" then
stop_sec_1 <= stop_sec_1 + 1;
end if;
if stop_sec_2 = "0110" then
stop_sec_2 <= "0000" ;
elsif stop_sec_1 = "1010" then
stop_sec_2 <= stop_sec_2 + 1;
end if;
if stop_min_1 = "1010" then--分进位
stop_min_1 <= "0000" ;
elsif stop_sec_2 = "1010" then
stop_min_1 <= stop_min_1 + 1;
end if;
if stop_min_2 = "1010" then
stop_min_2 <= "0000" ;
elsif stop_min_1 = "1010" then
stop_min_2 <= stop_min_2 + 1;
end if;
elsif not (stat(2) = '1') then--如果为其他状态各位清零
stop_mil_1 <= "0000";
stop_mil_2 <= "0000";
stop_sec_1 <= "0000";
stop_sec_2 <= "0000";
stop_min_1 <= "0000";
stop_min_2 <= "0000";
end if;
end if;
end process stop ;
end architecture one;
参考文献：
1.EDA技术实用教程.潘松、黄继业主编.科学出版社.2002

第2个回答 2019-06-27

是设置初始时钟吗,有一个CLK的引脚可以用.

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