已知器件74161管脚及功能如图,试用Verilog had 实现该器件

Question

如题所述

Answer 1

module counter74161(cep,cet,pe,d,cp,cr,q,tc);
input cep,cet,pe,cp,cr;
input [3:0]d;
output tc;
output [3:0]q
reg [3:0]q;
wire ce;
assign ce=cep&cet;
assign tc=cet&(q==4'b1111);
always @ (posedge cp or negedge cr)
if(~cr)
q<=4'b0000;
else if(~pe)
q<=d;
else if(~ce)
q<=q;
else
q<=q+1'b1;
endmodule
4位二进制加计数器。。