...高手帮我用VHDL语言设计一个8线—3线优先编码器,必须执行正确的,谢 ...答:port(st,in0,in1,in2,in3,in4,in5,in6,in7:IN bit;yex,ys,y0,y1,y2:out bit);end p_encoder;architecture rtl of p_encoder is signal tmp_in:bit_vector(7 downto 0);signal tmp_out:bit_vector(4 downto 0);begin tmp_in <=in7&in6&in5&in4&in3&in2&in1&in0;proce...