第1个回答 2009-06-15
-File:speaker.vhd
--Designer:
--Module:
--Description:
--Simulator:MAX plusII 10.0.9/Window XP
--Date:
--Modify date:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity speaker is
Port ( clk1 : in std_logic;
tone1 : in integer range 0 to 2047; --音符选择参数值
spks : out std_logic); --驱动扬声器的音频信号
end speaker;
architecture Behavioral of speaker is
signal preclk:std_logic;
signal spk:std_logic;
begin
pulse1:process(clk1) --此进程对系统时钟分频
variable count:integer range 0 to 6;
begin
if clk1'event and clk1='1' then
count:=count+1;
if count<3 then
preclk<='1';
elsif count<6 then
preclk<='0';
else count:=0;
end if;
end if;
end process pulse1;
genspks:process(preclk,tone1) --此进程完成音符发声算法
variable count11:integer range 0 to 1024;
begin
if preclk'event and preclk='1' then
count11:=count11+1;
if count11=tone1 then
spk<=not spk;
count11:=0;
end if;
end if;
spks<=spk;
end process;
end Behavioral;
--File:speaker.vhd
--Designer:
--Module:
--Description:
--Simulator:MAX plusII 10.0.9/Window XP
--Date:
--Modify date:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dianziqin is
Port ( clk : in std_logic;
index : in STD_LOGIC_VECTOR(7 DOWNTO 0); --音符选择参数值
high : out std_logic;
code :out std_LOGIC_VECTOR(3 DOWNTO 0);
spk:out std_logic); --驱动扬声器的音频信号
end dianziqin;
architecture Behavioral of dianziqin is
COMPONENT tone IS
PORT(index : in std_logic_vector(7 downto 0); --音符输入
code : out std_logic_vector(3 downto 0); --音符显示
tone0 : out integer range 0 to 2047; --音符选择参数
high: out std_logic);
END COMPONENT;
COMPONENT speaker IS
PORT( clk1 : in std_logic;
tone1 : in integer range 0 to 2047; --音符选择参数值
spks : out std_logic);
END COMPONENT;
signal a:integer range 0 to 2047;
begin
u1:tone PORT MAP(index=>index,code=>code,tone0=>a,high=>high);
u2:speaker port map(clk1=>clk,tone1=>a,spks=>spk);
end Behavioral;
--File:tone.vhd
--Designer:
--Module:
--Description:
--Simulator:MAX plusII 10.0.9/Window XP
--Date:
--Modify date:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tone is
Port ( index : in std_logic_vector(7 downto 0); --音符输入
code : out std_logic_vector(3 downto 0); --音符显示
tone0 : out integer range 0 to 2047; --音符选择参数
high: out std_logic); --高音信号
end tone;
architecture Behavioral of tone is
begin
search :process(index) --此进程完成音符到音符的分频系数译码，音符的显示，高低音阶
begin
case index is
when "00000001" => tone0<=956;code<="0001";high<='0';
when "00000010" => tone0<=851;code<="0010";high<='0';
when "00000100" => tone0<=758;code<="0011";high<='0';
when "00001000" => tone0<=716;code<="0100";high<='0';
when "00010000" => tone0<=638;code<="0101";high<='0';
when "00100000" => tone0<=568;code<="0110";high<='0';
when "01000000" => tone0<=506;code<="0111";high<='0';
when "10000000" => tone0<=478;code<="0001";high<='1';
when others => NULL;
end case;
end process;
end Behavioral;
coder
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY coder IS
PORT(din:IN STD_LOGIC_VECTOR(3 downto 0);
dout:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END;
ARCHITECTURE bev OF coder IS
BEGIN
PROCESS(din)
BEGIN
CASE din(3 downto 0) IS
WHEN "0000"=> dout<="0111111";
WHEN "0001"=> dout<="0000110";
WHEN "0010"=> dout<="1011011";
WHEN "0011"=> dout<="1001111";
WHEN "0100"=> dout<="1100110";
WHEN "0101"=> dout<="1101101";
WHEN "0110"=> dout<="1111101";
WHEN "0111"=> dout<="0000111";
WHEN "1000"=> dout<="1111111";
WHEN "1001"=> dout<="1101111";
WHEN "1010"=> dout<="1110111";
WHEN "1011"=> dout<="1111100";
WHEN "1100"=> dout<="0111001";
WHEN "1101"=> dout<="1011110";
WHEN "1110"=> dout<="1111001";
WHEN "1111"=> dout<="1110001";
WHEN OTHERS=> NULL;
END CASE;
END PROCESS;
END;
Counter10
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY counter10 IS
PORT( clk:IN STD_LOGIC;
reset:IN STD_LOGIC;
din:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
c:OUT STD_LOGIC);
END counter10;
ARCHITECTURE bev OF counter10 IS
SIGNAL count:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
dout<=count;
PROCESS(clk,reset,din)
BEGIN
IF reset='0' THEN
count<=din;
c<='0';
ELSIF rising_edge(clk) THEN
IF count="1001" THEN
count<="0000";
c<='1';
ELSE
count<=count+1;
c<='0';
END IF;
END IF;
END PROCESS;
END bev;
Counter24
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY counter24 IS
PORT( clk:IN STD_LOGIC;
reset:IN STD_LOGIC;
din:IN STD_LOGIC_VECTOR(5 DOWNTO 0);
dout:OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END counter24;
ARCHITECTURE bev OF counter24 IS
SIGNAL count:STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN
dout<=count;
PROCESS(clk,reset,din)
BEGIN
IF reset='0' THEN
count<=din;
ELSIF rising_edge(clk) THEN
IF count(3 DOWNTO 0)="1001" THEN
count(3 DOWNTO 0)<="0000";
count(5 DOWNTO 4)<=count(5 DOWNTO 4)+1;
ELSE count(3 DOWNTO 0)<=count(3 DOWNTO 0)+1;
end if;
if count="100011" THEN count<="000000";
END IF;
END IF;
END PROCESS;
END bev;
Counter6
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY counter6 IS
PORT( clk:IN STD_LOGIC;
reset:IN STD_LOGIC;
din:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
dout:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
c:OUT STD_LOGIC);
END counter6;
ARCHITECTURE bev OF counter6 IS
SIGNAL count:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
dout<=count;
PROCESS(clk,reset,din)
BEGIN
IF reset='0' THEN
count<=din;
c<='0';
ELSIF rising_edge(clk) THEN
IF count="101" THEN
count<="000";
c<='1';
ELSE
count<=count+1;
c<='0';
END IF;
END IF;
END PROCESS;
END bev;
Dclock
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY dclock IS
PORT(clk:IN STD_LOGIC;
reset:IN STD_LOGIC;
soutl:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
south:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
moutl:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
mouth:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
hout:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
load:in STD_LOGIC;
sel:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
h:in std_logic_vector(2 downto 0);
l:in std_logic_vector(3 downto 0));
END dclock;
ARCHITECTURE bev OF dclock IS
COMPONENT fp40m IS
PORT(clk:IN STD_LOGIC;
fp:OUT STD_LOGIC);
END COMPONENT;
COMPONENT counter10 IS
PORT(clk:IN STD_LOGIC;
reset:IN STD_LOGIC;
din:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
c:OUT STD_LOGIC);
END COMPONENT;
COMPONENT counter6 IS
PORT(clk:IN STD_LOGIC;
reset:IN STD_LOGIC;
din:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
dout:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
c:OUT STD_LOGIC);
END COMPONENT ;
COMPONENT counter24 IS
PORT(clk:IN STD_LOGIC;
reset:IN STD_LOGIC;
din:IN STD_LOGIC_VECTOR(5 DOWNTO 0);
dout:OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END COMPONENT ;
SIGNAL c1,c2,c3,c4:STD_LOGIC;
SIGNAL doutsl,doutml:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL doutsh,doutmh:STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL douth:STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL rdoutsh,rdoutmh:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL rdouth:STD_LOGIC_VECTOR(7 DOWNTO 0);
signal s:std_logic_vector(2 downto 0);
BEGIN
s<=sel;
process(sel)
begin
if load='1' then
case s is
when "100"=> douth(5 downto 4)<=h(1 downto 0);
douth(3 downto 0)<=l(3 downto 0);
when "010"=> doutmh(2 downto 0)<=h(2 downto 0);
doutml(3 downto 0)<=l(3 downto 0);
when"001"=> doutsh(2 downto 0)<=h(2 downto 0);
doutsl(3 downto 0)<=l(3 downto 0);
when others=>null;
end case;
end if;
end process;
u1:counter10 PORT MAP(clk=>clk,reset=>reset,din=>doutsl,
dout=>soutl,c=>c1); --秒低位十进制计数
u2:counter6 PORT MAP(clk=>c1,reset=>reset,din=>doutsh(2 downto 0),
dout=>south(2 downto 0),c=>c2); --秒高位十进制计数
u3:counter10 PORT MAP(clk=>c2,reset=>reset,din=>doutml,
dout=>moutl,c=>c3); --分低位十进制计数
u4:counter6 PORT MAP(clk=>c3,reset=>reset,din=>doutmh(2 DOWNTO 0),
dout=>mouth(2 downto 0),c=>c4); --分高位十进制计数
u5:counter24 PORT MAP(clk=>c4,reset=>reset,din=>douth(5 DOWNTO 0),
dout=>hout); --时24进制计数
END bev;
Fm40m
LIBRARY IEEE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fp40m IS
PORT(clk:IN STD_LOGIC; --40Hz
fp:OUT STD_LOGIC);--1Hz
END fp40m;
ARCHITECTURE bev OF fp40m IS
BEGIN
PROCESS(clk)
VARIABLE cnt:INTEGER RANGE 0 TO 19;
BEGIN
IF clk'EVENT AND clk='1' THEN
cnt:=cnt+1;
IF cnt<=20 THEN
fp<='1';
ELSIF cnt<=40 THEN
fp<='0';
ELSE cnt:=0;
END IF;
END IF;
END PROCESS;
END bev;本回答被网友采纳