FPGA verilog实现键控数码管动态显示 急啊!!答:D1,D2,D3,Q,COM,Enable,clk );input [3:0] D0,D1,D2,D3;input Enable,clk;output [7:0] Q;output [3:0] COM;reg [3:0] COM;reg [7:0] Q;reg [3:0] Dn;reg [1:0] state;always@(posedge clk)begin state <= state + 2'b1;end always@(posedge clk)begin if(!En...