VHDL源程序编写74ls148优先编码器答:entity nand2 is port(e1,d0,d1,d2,d3,d4,d5,d6,d7:IN bit;q0,q1,q2,e0,gs:out bit);end nand2;architecture rtl of nand2 is signal q:std_logic_vector(2 downto 0);begin process(e1,d)variable d:std_logic_vector(7 downto 0);begin d:=d7&d6&d5&d4&d3&d2&d...